module led_control(clk,rst,led_Begin,rx_data,led);
input clk,rst,led_Begin;
input[7:0] rx_data;
output[7:0] led;
reg[7:0] led_on;
always @(posedge clk or negedge rst)
begin
		if(!rst)
			led_on<=8'b00000000;
		else if(led_Begin)
			led_on<=rx_data;
end
assign led=led_on;
endmodule